ST16C654
Quad UART with 64-Byte FIFO and Infrared (IrDA) Encoder/Decoder

特性

  • Compatibility with the Industry Standard ST16C454/554, ST68C454/554, TL16C554
  • 1.5 Mbps transmit/receive operation (24MHz)
  • 64 byte transmit FIFO
  • 64 byte receive FIFO with error flags
  • Automatic software/hardware flow control
  • Programmable Xon/Xoff characters
  • Independent transmit and receive control
  • Software selectable Baud Rate Generator pre-scaleable clock rates of 1X, 4X
  • Four selectable Transmit/Receive FIFO interrupt trigger levels
  • Standard modem interface or infrared IrDA encoder/decoder interface
  • Software flow control turned off optionally by any (Xon) RX character
  • Independent MIDI interface on 100 pin packages
  • 100-pin packages offer internal register FIFO monitoring and separate IrDA TX outputs
  • Sleep mode ( 200mA stand-by)
  • Pb-Free, RoHS Compliant Versions Offered
应用

  • Portable Appliances
  • Telecommunication Network Routers
  • Ethernet Network Routers
  • Cellular Data Devices
  • Factory Automation and Process Controls
描述

The ST16C6541 is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface compatible with the ST16C554 and ST68C554. The 654 is an enhanced UART with 64 byte FIFO’s, automatic hardware/software flow control, and data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status, modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics.

The 654 is available in 64-pin TQFP, 68-pin PLCC, and 100-pin QFP packages. The 64-pin package offers the 16 interface mode which is compatible with the industry standard ST16C554. The 68 and 100 pin packages offer an additional 68 mode which allows easy integration with Motorola, and other popular microprocessors.

The ST16C654CQ64 (64 pin) offers three state interrupt control while the ST16C654DCQ64 provides constant active interrupt outputs. The 64 pin devices do not offer TXRDY/RXRDY outputs or the default clock select option (CLKSEL). The 100 pin packages offer faster channel status access by providing separate outputs for TXRDY and RXRDY, offer separate Infrared TX outputs and a musical instrument clock input (MIDICLK). The 654 combines the package interface modes of the 16C454/ 554 and 68/C454/554 series on a single integrated chip.

NOTE: 1 Covered by U.S. Patent #5,649,122.

For UART technical support or to obtain an IBIS model for this product, please email Exar's UART Technical Support group.
器件型号封装编码有害物质限制最低温度最高温度状态立刻购买申请样片
ST16C654IQ64LQFP64No-4085EOL
ST16C654CJ68-FPLCC68PLCC68070Active
ST16C654CQ100-FQFP100QFP100070Active
ST16C654CQ64-FLQFP64LQFP64070Active
ST16C654IJ68-FPLCC68PLCC68-4085Active
ST16C654IQ100-FQFP100QFP100-4085Active
ST16C654IQ64-FLQFP64LQFP64-4085Active
器件状态注释
Active（在售）-该器件可用于销售，标准产品
EOL(停产)-该器件不再生产,库存中可能有也可能没有存货
CF(联系工厂)-该器件仍然在销售，但是客户应该与相关工厂检查是否供货。适用于有较长交货期的情况。
PRE(准备投产)-该器件还未上市或者此型号还仅是用于样产的早期版本/样品阶段。
OBS(废弃)-器件不再生产，并停止订购。
NRND(不推荐用于新设计中)-不推荐在新设计中选择该器件。
规格
频道4
中央处理器接口Intel or Motorola
数据传输速率@5/3.3/2.5V1.5/0.5/na
发送器/接收器FIFO(Bytes)64/64
发送器/接收器FIFOCtrsNo
发送器/接收器FIFOINT Trig4 Levels/ 4 Levels
自动RTS/CTSYes
IrDa供应Yes
5VTol输入No
电压供应2.97 - 5.5
封装PLCC-68, QFP-100, LQFP-64
文档
???
Datasheet
Version 5.0.2
八月 2005
1.08 MB
ISA Eval Board Schematic
Version 1.1.0
九月 2007
187.38 KB
????
DAN-107, Interfacing 16Cxxx UARTs to a CPU
Version 1.0.0
八月 1999
32.43 KB
DAN-133, EXAR's ST16C554 vs TL16C554
Version 1.0.0
四月 2002
94.42 KB
DAN-134, EXAR's ST16C654 vs. TL16C754B
Version 1.0.0
六月 2002
72.50 KB
General UART Application Note
Version 1.0.0
十二月 1996
39.81 KB
AN-204, UART Sleep Mode
Version 1.0.0
六月 2010
511.72 KB
??
Evaluation Board User's Manual
Version 2.0.0
八月 2003
17.28 KB
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